Write a simple Verilog code to extend a 4-bit signed number to 8-bit signed number (extended from MSB). Draw a simple block diagram to show the extension.

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[10 pt] Problem 2

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Write a simple Verilog code to truncate from 8-bit unsigned number to 4-bit unsigned number (truncate from MSB and keep the LSBs). Draw a simple block diagram to show the extension.

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[20 pts] Problem 3

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How would we connect multiple 128K× 8-bit memory components to make a 128K×32-bit memory?

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- [5] First explain how many address bits and data bits are needed for a 128K×8-bit module, and how many address bits and data bits a 128K × 32-bit module needs?
- [8] Draw a detailed block diagram, with connections and details in memory blocks to build your 128K×32-bit memory from 128K×8-bit memory modules.
- [7] Write a Verilog model that creates this 128K × 32-bit memory module by instantiating and connecting multiple 128K× 8-bit modules.
- [5] Draw a detail block diagram for this comparator with input and output signals and intermediate blocks.
- [5] Write Verilog for this comparator (signed input: in0, in1, signed output: low, high)
- [5] Explain what is the critical path in your design.

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[15 pt] Problem 4

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Design a comparator that takes two 5-bit signed numbers as Input and Output is two numbers Low and High. **For example, if the two input numbers are 20 and 12 then Low is 12 and High is 20. **

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[20 pt] Problem 5

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Design a circuit that computes the summation of square magnitude of two 64 elements **a _{i}** and

**b**such that

_{i}**p**(where i is the index between 0 to 63).

_{i}=a_{i}^{2}+b_{i}^{2}**a**and

_{i}**b**have been stored in separate SSRAMS memories and the result

_{i}**p**is to be written into a third SSRAM. Assume that computation is started by an input signal,

_{i}**go**that is high for one clock cycle. When all 64 elements of

**pi**are computed the output signal

**done**is to be set to be and then the process starts over. Assume

**a**and

_{i}**b**

_{i }_{ }are 16-bit integer values.

**There is only one multiplier and one adder available (each one can take 2 input and have one output), you need to design a state machine to perform the operations sequentially.**

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The inputs for this circuit are:** go, ****a _{i}** and

**b**

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The outputs for this circuit are:** done **and **p _{i}**

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